P-A-3-45

Number of Bad Rocs: 0
Total number bad/defective pixels: 31
Percent Bad Bump Bonds (Electrical): 0.03%
Grade: A
Timeable: Yes
RTD temperature during testing: Not Set
Number of pXar errors during testing: Not Set
Double Columns below 95% efficiency: Not Set
Double Columns below 98% efficiency: Not Set
Double Columns below 0.60 uniformity: Not Set
Double Columns above 1.50 uniformity: Not Set
Next Testing Step: Full test at -20C
Official name of position: Not Set
Full Test at 17C Full Test at -20C X-ray Testing Thermal Cycling

Run at -300V

Unaddressable &
Unmaskable Pix
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 Bad Bumps (elec)
ROC02
ROC13
ROC20
ROC30
ROC40
ROC51
ROC62
ROC70
ROC151
ROC142
ROC130
ROC120
ROC113
ROC107
ROC91
ROC81
 Dead Pix
ROC00
ROC10
ROC20
ROC32
ROC43
ROC51
ROC60
ROC70
ROC150
ROC141
ROC130
ROC120
ROC110
ROC100
ROC91
ROC80
Vcal Thresh Defect Pix
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 IV Criteria
I(V=150) < 2uAI(V=150)/I(V=100) < 10
On Wafer:

PASS

PASS

Bare Module:

PASS

PASS

Fully Assembled:

PASS

PASS

Module at FNAL (-20C):

PASS

PASS

X-Ray Slope
ROC0 
ROC1 
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ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 X-Ray Offset
ROC0 
ROC1 
ROC2 
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ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
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ROC9 
ROC8 
 Lowest DC Uniformity
ROC0 
ROC1 
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ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
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ROC12 
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 Highest DC Uniformity
ROC0 
ROC1 
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ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 Lowest DC Efficiency
(Low Rate)
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 Lowest DC Efficiency
(High Rate)
ROC0 
ROC1 
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ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 

2015-07-30 16:26:09
2015-07-30 15:24:09 2015-07-30 15:22:37 Performed Full FPIXTest on 07/30/2015 10:28 pm FNAL time - Xuan

FPIXTest Results Output Directory:
P-A-3-45_ElComandanteTest_2015-07-30_10h28m_1438270124
2015-11-20 14:49:15 Next Testing Step set to Full test at -20C by Petra

2015-07-30 16:23:53
breakdown=579.827586207

2015-07-30 16:23:54
BB3_rescaledThr
2015-07-30 16:23:54
PixelAlive_PixelAlive
2015-07-30 16:23:54
PixelAlive_MaskTest
2015-07-30 16:23:54
PixelAlive_AddressDecodingTest
2015-07-30 16:23:54
PhOptimization_PH_mapLowVcal
2015-07-30 16:23:54
PhOptimization_PH_mapHiVcal
2015-07-30 16:23:54
Scurves_sig_scurveVcal_Vcal
2015-07-30 16:23:54
Scurves_thr_scurveVcal_Vcal
2015-07-30 16:23:54
Trim_thr_TrimThrFinal_vcal
2015-07-30 16:23:54
Trim_TrimMap
2015-07-30 16:23:54
Vana=[89, 80, 74, 84, 80, 76, 80, 89, 80, 81, 75, 85, 86, 85, 95, 90]

2015-07-30 16:23:54
Iana=[24.5, 24.5, 22.1, 22.9, 24.5, 22.9, 25.3, 24.5, 23.7, 23.7, 24.5, 25.3, 25.3, 24.5, 23.7, 24.5]

2015-07-30 16:23:54
VthrComp=130, CalDel=52

2015-07-30 16:23:54
VthrComp=126, CalDel=53

2015-07-30 16:23:54
VthrComp=114, CalDel=54

2015-07-30 16:23:54
VthrComp=122, CalDel=51

2015-07-30 16:23:54
VthrComp=136, CalDel=51

2015-07-30 16:23:54
VthrComp=104, CalDel=53

2015-07-30 16:23:54
VthrComp=109, CalDel=56

2015-07-30 16:23:54
VthrComp=115, CalDel=51

2015-07-30 16:23:54
VthrComp=126, CalDel=51

2015-07-30 16:23:54
VthrComp=147, CalDel=57

2015-07-30 16:23:54
VthrComp=121, CalDel=51

2015-07-30 16:23:54
VthrComp=126, CalDel=53

2015-07-30 16:23:54
VthrComp=143, CalDel=51

2015-07-30 16:23:54
VthrComp=133, CalDel=51

2015-07-30 16:23:54
VthrComp=105, CalDel=51

2015-07-30 16:23:54
VthrComp=120, CalDel=51

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