M-J-4-38

Number of Bad Rocs: 2
Total number bad/defective pixels: 14195
Percent Bad Bump Bonds (Electrical): 0%
Grade: C
Grades that were not A:
   ROC3: Grade C; biggest contribution: 4160 dead pixels
   ROC5: Grade C; biggest contribution: 4160 dead pixels
   ROC6: Grade C; biggest contribution: 4160 dead pixels
   ROC7: Grade C; biggest contribution: 1565 VCal threshold defect pixels
   X-Ray: I
ROC failure modes:
   ROC3: Dead DC w/ bad Trim
   ROC5: Zombie
   ROC6: Zombie
   ROC7: Dead DC w/ bad Trim
Timeable: Yes
RTD temperature during testing: -17C
Number of pXar errors during testing: 4
Double Columns below 95% efficiency: Not Set
Double Columns below 98% efficiency: Not Set
Double Columns below 0.60 uniformity: Not Set
Double Columns above 1.50 uniformity: Not Set
Next Testing Step: Rejected
Official name of position: Not Set
Full Test at 17C Full Test at -20C X-ray Testing Thermal Cycling

Run at -300V

Unaddressable &
Unmaskable Pix
ROC00
ROC10
ROC20
ROC30
ROC40
ROC50
ROC60
ROC70
ROC150
ROC140
ROC130
ROC120
ROC110
ROC100
ROC90
ROC80
 Bad Bumps (elec)
ROC00
ROC10
ROC20
ROC30
ROC40
ROC50
ROC60
ROC70
ROC150
ROC140
ROC130
ROC120
ROC110
ROC101
ROC90
ROC80
 Dead Pix
ROC00
ROC10
ROC20
ROC34160
ROC40
ROC54160
ROC64160
ROC7149
ROC150
ROC140
ROC130
ROC120
ROC110
ROC100
ROC90
ROC80
Vcal Thresh Defect Pix
ROC00
ROC10
ROC20
ROC30
ROC40
ROC50
ROC60
ROC71565
ROC150
ROC140
ROC130
ROC120
ROC110
ROC100
ROC90
ROC80
 IV Criteria
I(V=150) < 2uAI(V=150)/I(V=100) < 10
On Wafer:

PASS

PASS

Bare Module:

PASS

PASS

Fully Assembled:

PASS

PASS

Module at FNAL (+17C):

PASS

PASS

Module at FNAL (-20C):

PASS

PASS

X-Ray Slope
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 X-Ray Offset
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 Lowest DC Uniformity
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 Highest DC Uniformity
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 Lowest DC Efficiency
(Low Rate)
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 
 Lowest DC Efficiency
(High Rate)
ROC0 
ROC1 
ROC2 
ROC3 
ROC4 
ROC5 
ROC6 
ROC7 
ROC15 
ROC14 
ROC13 
ROC12 
ROC11 
ROC10 
ROC9 
ROC8 

2016-02-26 13:26:48 Next Testing Step set to Thermal cycling by drberry
2016-02-26 17:26:42 Next Testing Step set to Debugging by drberry
2016-02-29 13:04:56 Next Testing Step set to Debugging by drberry
2016-02-29 13:04:56 High Idig. No Iana draw ROCs 5 and 6. High Iana draw for whole module, suspect Iana short in ROC5 or ROC6. Digital voltage on ROC5 and ROC6 is okay. Cannot decoding TBM Core A Port 1. Replace TBM?     --drberry
2016-03-01 16:19:20 Next Testing Step set to Full test at 17C by drberry
2016-03-01 16:19:20 No data or Iana from ROCs 5 and 6. Squished tornado from ROC3, ROC3 requires additional Vana. Bad DC46 ROC3. Bad DC28 ROC7. Low Vdig ROC7 (1.94V).     --drberry
2016-03-02 12:54:44 Test results and config files can be found in: M-J-4-38_FPIXTest-17C-FNAL-160302-1009_2016-03-02_10h09m_1456934972
2016-03-02 14:18:35 Test results and config files can be found in: M-J-4-38_FPIXTest-17C-FNAL-160302-1009_2016-03-02_10h09m_1456934972
2016-03-02 15:06:56 Test results and config files can be found in: M-J-4-38_FPIXTest-m20C-FNAL-160302-1156_2016-03-02_11h56m_1456941391
2016-03-02 15:10:05 Completed post-assembly tests: Full test at 17C, Full test at -20C, by Xuan
2016-03-02 15:10:05 Next Testing Step set to Final Judgement by Xuan
2016-03-03 14:23:55 Set to Rejected by Petra
2016-03-03 14:23:55 GradeC: three bad ROCs and another 1-2 dead dcols.     --Petra
2016-08-17 19:56:20 Test results and config files can be found in: M-J-4-38_FPIXTest-m20C-FNAL-160302-1156_2016-03-02_11h56m_1456941391

2016-03-02 11:56:00
breakdown=605.0

2016-03-02 11:56:00
BB3_rescaledThr
2016-03-02 11:56:00
PixelAlive_PixelAlive
2016-03-02 11:56:00
PixelAlive_MaskTest
2016-03-02 11:56:00
PixelAlive_AddressDecodingTest
2016-03-02 11:56:00
PhOptimization_PH_mapLowVcal
2016-03-02 11:56:00
PhOptimization_PH_mapHiVcal
2016-03-02 11:56:00
Scurves_sig_scurveVcal_Vcal
2016-03-02 11:56:00
Scurves_thr_scurveVcal_Vcal
2016-03-02 11:56:00
Trim_TrimMap
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
Vana=[78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78, 78]

2016-03-02 11:56:00
Iana=[24.5, 23.7, 22.9, 18.8, 24.5, 18.0, 18.8, 22.9, 24.5, 24.5, 24.5, 23.7, 23.7, 22.9, 24.5, 24.5]

2016-03-02 11:56:00
VthrComp=51, CalDel=143

2016-03-02 11:56:00
VthrComp=51, CalDel=136

2016-03-02 11:56:00
VthrComp=51, CalDel=144

2016-03-02 11:56:00
VthrComp=51, CalDel=96

2016-03-02 11:56:00
VthrComp=51, CalDel=141

2016-03-02 11:56:00
VthrComp=49, CalDel=96

2016-03-02 11:56:00
VthrComp=49, CalDel=96

2016-03-02 11:56:00
VthrComp=51, CalDel=146

2016-03-02 11:56:00
VthrComp=51, CalDel=138

2016-03-02 11:56:00
VthrComp=51, CalDel=150

2016-03-02 11:56:00
VthrComp=51, CalDel=132

2016-03-02 11:56:00
VthrComp=51, CalDel=144

2016-03-02 11:56:00
VthrComp=51, CalDel=144

2016-03-02 11:56:00
VthrComp=51, CalDel=146

2016-03-02 11:56:00
VthrComp=51, CalDel=140

2016-03-02 11:56:00
VthrComp=51, CalDel=143

2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00
2016-03-02 11:56:00